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HN27C4001G Series
524288-word x 8-bit CMOS UV Erasable and Programmable ROM
Description
The Hitachi HN27C4001G is a 4-Mbit ultraviolet erasable and electrically programmable ROM, featuring high speed and low power dissipation. Fabricated on advanced fine process and high speed circuitry technique, the HN27C4001G makes high speed access time possible. Therefore, it is suitable for high speed microcomputer systems. The HN27C4001G offers high speed programming using page programming mode.
Features
* High speed Access time: 100 ns/120 ns/150 ns (max) * Low power dissipation Standby mode: 5 W(typ) Active mode: 35 mW/MHz (typ) * Fast high reliability page programming and fast high-reliability programming Programming voltage: +12.5 V D.C. Program time: 3.5 sec (min) (Theoretical in page programming) * Inputs and outputs TTL compatible during both read and program modes * Pin arrangement 32-pin JEDEC standard * Device identifier mode Manufacturer code and device code
Ordering Information
Type No. HN27C4001G-10 HN27C4001G-12 HN27C4001G-15 Access Time 100 ns 120 ns 150 ns Package 600 mil 32-pin Cerdip (DG-32A)
HN27C4001G Series
Pin Arrangement
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A18 A17 A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
Pin Description
Pin Name A0-A18 I/O0 - I/O7 CE OE VCC VPP VSS Function Address Input / output Chip enable Output enable Power supply Programming power supply Ground
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HN27C4001G Series
Block Diagram
A6 - A9 A11 - A18
X-Decoder
4096 x 1024 Memory Matrix
I/O0 I/O7
Input Data Control
Y-Gating Y-Decoder
CE OE VCC VPP H VSS H : High Threshold Inverter H A0 - A5, A10
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HN27C4001G Series
Mode Selection
Mode Read Output disable Standby Page program Page program set Page data latch Page program Page program verify Pin CE (22) OE (24) A9 (26) VPP (1) VIL VIL VIH VIH VIL VIL VIH VIL VIH X VH VH
*2 *2
VCC (32) VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
I/O (13 - 15, 17 - 21) Dout High-Z High-Z High-Z Din High-Z Dout High-Z Din Dout Dout High-Z Code
X X X X X X X X X X X X VH
*2
VSS - VCC VSS - VCC VSS - VCC VPP VPP VPP VPP VCC VPP VPP VPP VPP VSS - V CC
VIH VIL VIH VIH VIL VIL VIH VIL
Page program reset VIH Word program Program Program verify Optional verify Program inhibit Identifier Notes: 1. X: Don't care. 2. VH : 12.0 V 0.5 V. VIL VIH VIL VIH VIL
Absolute Maximum Ratings
Parameter All input and output voltages Voltage on Pin A9 and OE Vpp voltage Vcc voltage
*1 *1 *1
Symbol Vin, Vout VID VPP VCC Topr Tstg Tbias
*3
Value -0.6 to +7.0 -0.6 to +13.0 -0.6 to +13.5 -0.6 to +7.0 0 to +70 -65 to +125 -20 to +80
*2 *2
Unit V V V V C C C
Operating temperature range Storage temperature range
Storage temperature range under bias
Notes: 1. Relative to VSS . 2. Vin, Vout, V ID min = -2.0 V for pulse width 20 ns. 3. Storage temperature range of device before programming.
4
HN27C4001G Series
Capacitance (Ta = 25C, f = 1 MHz)
Parameter Input capacitance Output capacitance Symbol Cin Cout Min -- -- Typ -- -- Max 12 20 Unit pF pF Test Conditions Vin = 0 V Vout = 0 V
Read Operation
DC Characteristics (VCC = 5 V 10%, VPP = VSS to VCC, Ta = 0 to +70C)
Parameter Input leakage current Output leakage current Vpp current Standby V CC current Symbol I LI I LO I PP1 I SB1 I SB2 Operating VCC current I CC1 I CC2 Input voltage VIL VIH Output voltage VOL VOH Min -- -- -- -- -- -- -- -0.3 2.2 -- 2.4
*1
Typ -- -- 1 -- 1 -- -- -- -- -- --
Max 2 2 20 1 20 30 100 0.8 VCC + 1 0.45 --
*2
Unit A A A mA A mA mA V V V V
Test Conditions Vin = 5.5 V Vout = 5.5 V/0.45 V Vpp = 5.5 V CE = VIH CE = VCC 0.3 V Iout = 0 mA, f = 1 MHz Iout = 0 mA, f = 10 MHz
I OL = 2.1 mA I OH = -400 A
Notes: 1. VIL min = -1.0 V for pulse width 50 ns. VIL min = -2.0 V for pulse width 20 ns. 2. VIH max = VCC +1.5 V for pulse width 20 ns. If V IH is over the specified maximum value, read operation cannot be guaranteed.
5
HN27C4001G Series
AC Characteristics (VCC = 5 V 10%, VPP = VSS to VCC, Ta = 0 to +70C) Test Conditions * * * * Input pulse levels: 0.45 to 2.4 V Input rise and fall time: 10 ns Output load: 1TTL Gate + 100 pF Reference levels for measuring timing: 0.8 V, 2.0 V
HN27C4001 -10 Parameter Symbol Min -- -- -- 0 5 Max 100 100 60 35 -- -12 Min -- -- -- 0 5 Max 120 120 60 40 -- -15 Min -- -- -- 0 5 Max 150 150 70 50 -- Unit Test Conditions ns ns ns ns ns CE = OE = VIL OE = VIL CE = VIL CE = VIL CE = OE = VIL
Address to output delay t ACC CE to output delay OE to output delay OE high to output float Note:
*1
t CE t OE t DF t OH
Address to output hold
1. t DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
Read Timing Waveform
Address
CE
Standby Mode tCE
Active Mode
Standby Mode
OE tOE tACC Data Out Data Out Valid tOH tDF
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HN27C4001G Series
Fast High-Reliability Page Programming
This device can be applied the high performance page programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. Page Program Set Apply 12 V to OE pin after applying 12.5 V to VPP to set a page program mode. The device operates in a page program mode until reset. Page Program Reset Set VPP to VCC level or less to reset a page program mode.
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HN27C4001G Series
START SET PAGE PROG. LATCH MODE VPP = 12.5 0.3 V, VCC = 6.25 0.25 V OE = 12.0 0.5 V Address = 0 n=0 m=0 Latch Address + 1 m+1 NO Address m
m = 8? YES n+1 n
Address + 1
Address
SET PAGE PROG./VERIFY MODE VPP = 12.5 0.3 V, VCC = 6.25 0.25 V Program tPW = 50 s 5% NOGO
VERIFY GO NO LAST Address? YES
n = 10? YES
NO
SET READ MODE VCC = 5.0 0.5 V, VPP = VCC READ All Address GO END FAIL NOGO
Fast High-Reliability Page Programming Flowchart
8
HN27C4001G Series
DC Characteristics (VCC = 6.25 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C)
Parameter Input leakage current Output voltage during verify Symbol I LI VOL VOH Operating VCC current Input voltage I CC VIL VIH VH VPP supply current I PP Min -- -- 2.4 -- -0.1 2.2 11.5 --
*5
Typ -- -- -- -- -- -- 12.0 --
Max 2 0.45 -- 50 0.8 VCC + 0.5 12.5 70
*6
Unit A V V mA V V V mA
Test Conditions Vin = 6.5 V/ 0.45 V I OL = 2.1 mA I OH = -400 A
CE = VIL
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after V PP . 2. VPP must not exceed 13.5 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.5 V. 4. Do not alter VPP either V IL to 12.5 V or 12.5 V to VIL when CE = low. 5. VIL min = -0.6 V for pulse width 20 ns. 6. If V IH is over the specified maximum value, programming operation cannot be guaranteed.
9
HN27C4001G Series
AC Characteristics (VCC = 6.25 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C)
Test Conditions * Input pulse levels: 0.45 to 2.4 V * Input rise and fall time: 20 ns * Reference levels for measuring timing: Inputs: 0.8 V, 2.0 V Outputs: 0.8 V, 2.0 V
Parameter Address setup time OE setup time Data setup time Address hold time Data hold time OE high to output float delay VPP setup time VCC setup time CE programming pulse width CE setup time Data valid from OE CE pulse width during data latch OE = VH setup time OE = VH hold time VPP hold time
*2
Symbol t AS t OES t DS t AH t DH t DF
*1
Min 2 2 2 0 2 0 2 2 47.5 2 0 1 2 2 1
Typ -- -- -- -- -- -- -- -- 50.0 -- -- -- -- -- --
Max -- -- -- -- -- 130 -- -- 52.5 -- 150 -- -- -- --
Unit s s s s s ns s s s s ns s s s s
Test Conditions
t VPS t VCS t PW t CES t OE t LW t OHS t OHH t VRS
Notes: 1. t DF is defined as the time at which the output achieves the open circuit conditions and data is no longer driven. 2. Page program mode will be reset when V PP is set to VCC or less.
10
HN27C4001G Series
Fast High-Reliability Page Programming Timing Waveform
Page Program Mode Program Data Latch A3 - A18 tAH tAS A0 - A2 0 1 tDH tDS Data tVPS VPP VPP VCC tVCS VCC+1.25 VCC VCC CE tLW tOHS tOHH tCES tPW tOES
0 Data in Stable
Page Program
Program Verify
tAS 7 0 tOE
tAH
1
7
tDF 7 0 1 7
1
Data Out Valid
VH tVRS OE VIH VIL
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HN27C4001G Series
Fast High-Reliability Programming
This device can be applied the fast high-reliability programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data.
START SET PROG./VERIFY MODE VPP = 12.5 0.3 V, VCC = 6.25 0.25 V Address = 0 n=0 n+1 n
Program tPW = 50 s 5% Address + 1 Address VERIFY GO NO LAST address? n = 10? YES NO NOGO
YES SET READ MODE VCC = 5.0 0.5 V, VPP = VCC READ all address GO END NOGO
FAIL
Fast High-Reliability Programming Flowchart
12
HN27C4001G Series
DC Characteristics (VCC = 6.25 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C)
Parameter Input leakage current VPP supply current Operating VCC current Input voltage Symbol I LI I PP I CC VIL VIH Output voltage VOL VOH Min -- -- -- -0.1 2.2 -- 2.4
*5
Typ -- -- -- -- -- -- --
Max 2 40 50 0.8 VCC + 0.5 0.45 --
*6
Unit A mA mA V V V V
Test Conditions Vin = 6.5 V/ 0.45 V CE = VIL
I OL = 2.1 mA I OH = -400 A
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after V PP . 2. VPP must not exceed 13.5 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.5 V. 4. Do not alter VPP either V IL to 12.5 V or 12.5 V to VIL when CE = low. 5. VIL min = -0.6 V for pulse width 20 ns. 6. If V IH is over the specified maximum value, programming operation cannot be guaranteed.
13
HN27C4001G Series
AC Characteristics (VCC = 6.25 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C)
Test Conditions * Input pulse levels: 0.45 to 2.4 V * Input rise and fall time: 20 ns * Reference levels for measuring timing: Inputs: 0.8 V, 2.0 V Outputs: 0.8 V, 2.0 V
Parameter Address setup time OE setup time Data setup time Address hold time Data hold time OE to output float delay VPP setup time VCC setup time CE programming pulse width Data valid from OE Note: Symbol t AS t OES t DS t AH t DH t DF
*1
Min 2 2 2 0 2 0 2 2 47.5 0
Typ -- -- -- -- -- -- -- -- 50.0 --
Max -- -- -- -- -- 130 -- -- 52.5 150
Unit s s s s s ns s s s ns
Test Conditions
t VPS t VCS t PW t OE
1. t DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
14
HN27C4001G Series
Fast High-Reliability Programming Timing Waveform
Program Address t AS Data tDS VPP VPP VCC t VPS VCC VCC +1.25 VCC t VCS CE Data In Stable t DH t AH Program Verify
Data Out Valid t DF
t PW OE
t OES
t OE
Optional Page Programming
This device can be applied the optional page programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. This programming algorithm is the combination of page programming and byte verify. It can avoid the increase of programming verify time when a programmer with slow machine cycle is used, and shorten the total programming time. Regarding the timing specifications for page programming and byte verify, please refer to the specifications for fast high-reliability page programming and fast high-reliability programming.
15
HN27C4001G Series
START SET PAGE PROG. LATCH MODE VPP = 12.5 0.3 V, VCC = 6.25 0.25 V OE = 12.0 0.5 V Address = 0 m=0 Latch Address + 1 m+1 Address m NO
A Address = 0 n=0
m = 8? YES
SET PAGE PROG. MODE VPP = 12.5 0.3 V, VCC = 6.25 0.25 V Address + 1 Address Program tPW = 50 s 5% GO
VERIFY NOGO n+1 n
NO
LAST Address?
YES PAGE PROG. RESET VPP = VCC = 6.25 0.25 V
Address + 1 Address
Program tPW = 50 s 5% NOGO
VERIFY GO NO LAST Address? YES
SET WORD PROG./VERIFY MODE VPP = 12.5 0.3 V, VCC = 6.25 0.25 V A
n = 10? YES
NO
SET READ MODE VCC = 5.0 0.5 V, VPP = VCC READ All Address GO END NOGO
FAIL
Optional Page Programming Flowchart
16
HN27C4001G Series
DC Characteristics (VCC = 6.25 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C)
Parameter Input leakage current Output voltage during verify Symbol I LI VOL VOH Operating VCC current Input voltage I CC VIL VIH VH Vpp supply current I PP Min -- -- 2.4 -- -0.1 2.2 11.5 --
*5
Typ -- -- -- -- -- -- 12.0 --
Max 2 0.45 -- 50 0.8 VCC + 0.5 12.5 70
*6
Unit A V V mA V V V mA
Test Conditions Vin = 6.5 V / 0.45 V I OL = 2.1 mA I OH = -400 A
CE = VIL
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after V PP . 2. VPP must not exceed 13.5 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.5 V. 4. Do not alter VPP either V IL to 12.5 V or 12.5 V to VIL when CE = low. 5. VIL min = -0.6 V for pulse width 20 ns. 6. If V IH is over the specified maximum value, programming operation cannot be guaranteed.
17
HN27C4001G Series
AC Characteristics (VCC = 6.25 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C)
Test Conditions * Input pulse levels: 0.45 to 2.4 V * Input rise and fall time: 20 ns * Reference levels for measuring timing: Inputs: 0.8 V, 2.0 V Outputs: 0.8 V, 2.0 V
Parameter Address setup time OE setup time Data setup time Address hold time Data hold time OE high to output float delay VPP setup time VCC setup time CE programming pulse width CE setup time Data valid from OE CE pulse width during data latch OE = VH setup time OE = VH hold time Page programming reset time VPP hold time
*2 *2
Symbol t AS t OES t DS t AH t DH t DF
*1
Min 2 2 2 0 2 0 2 2 47.5 2 0 1 2 2 1 1
Typ -- -- -- -- -- -- -- -- 50.0 -- -- -- -- -- -- --
Max -- -- -- -- -- 130 -- -- 52.5 -- 150 -- -- -- -- --
Unit s s s s s ns s s s s ns s s s s s
Test Conditions
t VPS t VCS t PW t CES t OE t LW t OHS t OHH t VLW t VRS
Notes: 1. t DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. Page program mode will be reset when V PP is set to VCC or less.
18
HN27C4001G Series
Option Page Programming Timing Waveform
Page program mode Program data latch Page program
Word program mode Program verify Program
A3 - A18 t AH t AS t AH t AS t AH
A0, A2 t DS
0
1 t DH
7 t DS
t DF
Data in stable
Data t VPS VPP VCC t VCS
0 Data in stable
1
7
Data out valid
t VPS t OE t DF
VPP
t VRS t VLW
VCC+ 1.25 VCC VCC t OHS t OHH t CES
t CES
CE t LW VH OE VIH VIL t PW
t OES t PW
Erase
Erasure of HN27C4001G is performed by exposure to ultraviolet light of 2537 A and all the output data are changed to "1" after this erasure procedure. The minimum integrated dose (i.e. UV intensity x exposure time) for erasure is 15 W* sec/cm2.
19
HN27C4001G Series
Mode Description
Device Identifier Mode The device identifier mode allows the reading out of binary codes that identify manufacturer and type of device, from outputs of EPROM. By this mode, the device will be automatically matched its own corresponding programming algorithm, using programming equipment. HN27C4001G Identifier Code
A0 (12) VIL VIH I/O7 (21) 0 0 I/O6 (20) 0 0 I/O5 (19) 0 1 I/O4 (18) 0 0 I/O (17) 0 0 I/O2 (15) 1 0 I/O1 (14) 1 0 I/O0 (13) 1 0
Identifier Manufacturer code Device code Notes: 1. 2. 3. 4.
Hex Data 07 20
VCC = 5.0 V 10% A9 = 12.0 V 0.5 V CE, OE = VIL A1 - A8, A10 - A18: Don't care.
20
HN27C4001G Series
Package Dimensions
HN27C4001G Series (DG-32A)
41.91 43.18 Max 32 17.00 14.66 15.51 Max 7.00 17
Unit: mm
1
2.54 Max
1.32
16 0.38 Min 15.24 5.89 Max 2.54 Min
2.54 0.25
0.48 0.10
0.11 0.25 + 0.05 -
0 - 10
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